add: documentation: memory

documentation/memory/frame.md

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+# FRAME
+
+Like [page](./page.md) but in physical memory space

documentation/memory/mmu.md

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+# Memory Management Unit (MMU)
+The MMU is a chip which translate virtual memory to physical memory. When you try to access to an address (/!\ only when you try to access) the MMU will get the physical address from the [pd](./page_directory.md).
+
+## How translate an address ?
+The address will be divid in 3 parts:
+- Page Directory index (10bit (cause 1024))
+- Page Table index (10bit (cause 1024 too))
+- offset (12bit cause page size = 4096)
+
+### Example
+
+**address**: 0b000100000011101011111011101101
+
+| Base   | PD index | PT index   | offset       |
+|--------|----------|------------|--------------|
+| Binary | 00010000 | 0011101011 | 111011101101 |
+| Decimal| 16       | 235        | 3821         |
+
+So to translate this address the MMU will get the 20 first bit of the value store at the 235th PTE of the 16th PDE and will replace the 20 first bit of the virtually address.

documentation/memory/page.md

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+# PAGE
+
+A page is a memory space with with a specific size (default 4096byte).

documentation/memory/page_directory.md

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+# PAGE DIRECTORY
+
+The page directory (or pd) is 
+
+
+## Indexed Size
+A PD can store 1024 PT, each PT index 1024 * 4096Byte = 4MB of address, so a PD can index 1024 * 4MB = 4GB.

documentation/memory/page_table.md

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+# PAGE TABLE
+
+A page table (or PT) is an 1024 array of 32bit value(Page Table Entry (or PTE)). The address of the PT is store in the [PD](./page_directory.md).
+
+## Page Table Entry (PTE)
+The value is a 20 first bits of the [frame](./frame.md) address and the 12 last bit is for the flag.
+
+### Not used PTE value
+To say to the [MMU](./mmu.md) the page is currently not attribued to a frame you should put the (PTE index << 12)
+
+## Indexed Size
+Cause our kernel use 4096byte page and a PT can store 1024 value, each PT index 1024 * 4096Byte = 4MB of address.