core: remove apic.c and unused function in pic.c
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1640b2e125
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0812a06350
@ -1,69 +0,0 @@
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#include "apic.h"
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#include "cpuid.h"
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#include <cpuid.h>
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#include <stdbool.h>
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#include <stdint.h>
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#define IA32_APIC_BASE_MSR 0x1B
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#define IA32_APIC_BASE_MSR_BSP 0x100 // Processor is a BSP
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#define IA32_APIC_BASE_MSR_ENABLE 0x800
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/** returns a 'true' value if the CPU supports APIC
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* and if the local APIC hasn't been disabled in MSRs
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* note that this requires CPUID to be supported.
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*/
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bool check_apic()
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{
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static unsigned int eax, edx, unused;
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__get_cpuid(1, &eax, &unused, &unused, &edx);
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return edx & CPUID_FEAT_EDX_APIC;
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}
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/* Set the physical address for local APIC registers */
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static void cpu_set_apic_base(uintptr_t apic)
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{
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uint32_t edx = 0;
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uint32_t eax = (apic & 0xfffff0000) | IA32_APIC_BASE_MSR_ENABLE;
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#ifdef __PHYSICAL_MEMORY_EXTENSION__
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edx = (apic >> 32) & 0x0f;
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#endif
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cpu_set_msr(IA32_APIC_BASE_MSR, eax, edx);
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}
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/**
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* Get the physical address of the APIC registers page
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* make sure you map it to virtual memory ;)
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*/
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static uintptr_t cpu_get_apic_base(void)
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{
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uint32_t eax, edx;
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cpu_get_msr(IA32_APIC_BASE_MSR, &eax, &edx);
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#ifdef __PHYSICAL_MEMORY_EXTENSION__
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return (eax & 0xfffff000) | ((edx & 0x0f) << 32);
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#else
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return (eax & 0xfffff000);
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#endif
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}
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static uint32_t read_apic_register(uint32_t reg)
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{
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return *((volatile uint32_t *)(cpu_get_apic_base()) + reg);
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}
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static void write_apic_register(uint32_t reg, uint32_t value)
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{
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*((volatile uint32_t *)(cpu_get_apic_base() + reg)) = value;
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}
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void enable_apic(void)
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{
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/* Hardware enable the Local APIC if it wasn't enabled */
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cpu_set_apic_base(cpu_get_apic_base());
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/* Set the Spurious Interrupt Vector Register bit 8 to start receiving
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* interrupts */
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write_apic_register(0xF0, read_apic_register(0xF0) | 0x100);
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}
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@ -56,12 +56,6 @@ void pic_remap(int offset_master, int offset_slave)
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outb(PIC2_DATA, a2);
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}
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void pic_disable(void)
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{
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outb(PIC1_DATA, 0xff);
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outb(PIC2_DATA, 0xff);
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}
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void pic_send_eoi(uint8_t irq)
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{
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if (irq >= 8)
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